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PAS106BCB-283 PAS106BBB-283
PAS106BCB-283 SINGLE-CHIP CMOS CIF COLOR DIGITAL IMAGE SENSOR PAS106BBB-283 SINGLE-CHIP CMOS CIF B&W DIGITAL IMAGE SENSOR General Description
The PAS106BCB-283/PAS106BBB-283 is a highly integrated CMOS active-pixel image sensor that has a CIF resolution of 356H x 292V. To have an excellent image quality, the PAS106BCB-283/PAS106BBB-283 outputs 10-bit RGB raw data through a parallel data bus. It is available in color or monochrome in 28-pin LCC package. The PAS106BCB-283/PAS106BBB-283 can be programmed to set the exposure time for different luminance condition via I2CTM serial control bus. By programming the internal register sets, it performs on-chip frame rate adjustment, offset correction DAC and programmable gain control.
Features
CIF(356 x 292 pixels) resolution, ~1/5" Lens Bayer-RGB color filter array On-chip 10-bit pipelined A/D converter Output formats: 10-bit parallel RGB raw data On-chip 6-bit (1 sign bit+ 5 magnitude bit) background compensation DAC On-chip programmable gain amplifier
q q
Key Specification
Supply Voltage Array formate Optical format Pixel Size Frame rate System clock Max. pixel rate Sensitivity PGA gain Color filter Exposure Time Scan Mode S/N Ratio Package 3.3V + 5% 356(H) x 292(V) ~1/5 " 7.25m x 7.25m 30 fps Up to 48 MHz 4 MHz 1.0V/lux-sec 31.6 dB ma x. RGB Bayer Pattern ~ Frame time to 1/160000 Progressive
>45dB
5-bit color gain amplifier(x4) 5-bit global gain amplifier (x5)
Continuous variable frame time(1/2sec~1/30sec) Continuous variable exposure time I2C Interface Digitally programmable registers Single 3.3V supply voltage
100 mW low power dissipation
28 pin LCC
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1. Pin Assignment
PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PIN NAME VLRST VSSA VRB VRT VDDA VDDAY VSSAY CSB PXD<9> PXD<8> PXD<7> PXD<6> PXD<5> PXD<4> VDDQ VSSQ PXD<3> PXD<2> PXD<1> PXD<0> PXCLK HSYNC VSYNC SYSCLK SCL SDA VDDD VSSD Type BIAS GND BYPASS BYPASS PWR PWR GND IN OUT OUT OUT OUT OUT OUT PWR GND OUT OUT OUT OUT OUT OUT OUT IN IN I/O PWR GND Definition Fixed bias input voltage, 1.65V Analog ground Analog voltage reference Analog voltage reference Analog VDD, 3.3V Analog VDD, 3.3V Analog ground Chip select (Low active, chip disabled if high) Digital data output Digital data output Digital data output Digital data output Digital data output Digital data output Digital VDD, 3.3V Digital ground Digital data output Digital data output Digital data output Digital data output Pixel clock output Horizontal Synchronization clock Vertical Synchronization clock Master clock input I2C clock I2C bi-directional data Digital VDD, 3.3V Digital ground
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2. Block Diagram
Row Decoders
6-bit +/-1V DAC Sensor Array Color gain B,G1,G2,R Global gain 5-bits 5-bits X4 X5
CDS ckts Col. Decoders
cmd I2C Interface Register sets Timing & Digital Control 10-bit pipelined ADC
Pxo<9:0> PXCLK Vsync Hsync
SDA SCL SysClk
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3. Pixel Array And Pixel Color Pattern
The output image format of PAS106BCB-283/PAS106BBB-283 is CIF (352x288 pixel array). To provide the co-processor with the extra information it needs for interpolation at the edges of the pixel array, an border of 2 pixels on all 4 sides of the array are available. Fig 3.1. illustrates the pixel array and pixel color pattern.
30 dark pixel
30 dark pixel 20 R pixel
30 dark pixel
30 dark pixel 20 pixel
No filter
20 G pixel G
20 B pixel B
Dark pixel G2 R G2 R B G1 B G1 G2 R G2 R
R
Dark pixel G2 R G2 R B G1 B G1 G2 R G2 R
Row 293 Row 292
Array: 356(column)x 294(row)
294 row lines
B G1 B G1 G2 R G2 R B G1 B G1 Dark pixel
R 20 R pixel
G 20 G pixel
B 20 B pixel 30 dark pixel
No filter
B G1 B G1 G2 R G2 R B G1 B G1 Dark pixel
Row 1 Row 0
20 pixel
30 dark pixel
30 dark pixel
30 dark pixel 356 column lines
Fig 3.1. Pixel array and pixel color pattern
Note: 1. 2. 3. Pixel color pattern does not apply to monochrome sensor. Pixel read-out proceeds from left to right, and from bottom row to top row. Pixel array not drawn to scale.
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4. Output timing:
Fixed pixel clock for each line(row), 444pxclk. 4+4 blank pxclk for each line. ( See Fig 4.1. ) 1+1 Dark line for each frame.(See Fig 4.2. ) Dark line output format: Fig 4.3.
line time = 80+4+2+352+2+4 = 444 pxclks Hsync. xxx x x x x 2+352+2 pixels outx x x x B GB G 11 Pxclk_a Fig 4.1. Inter-line timing Vsync. Frame time (=294 lines) 80 Pxclks Dark Dark 80 pxclks x x x x 2+352+2 pixels out Note: "x" indicates don't care PXD[9:0]
80 Pxclks Dark B,G1,B,G1... G2,R,G2,R... Valid frame data (292 lines) Fig 4.2. Inter-frame timing 4+356+4=364 pxclks
Hsync.
Dark
Hsync 80 pxclks xxx x R G B
Hsync 80 pxclks No xxx x filfter 20 R pixels 20 G pixels 20 B pixels 20 pixels 28 dark pixels30 dark pixels dark pixels dark pixels 30 30 Note: "x" indicates don't care. Fig 4.3. Dark line output format
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5. I2C Bus
PAS106BCB-283/PAS106BBB-283 supports I2C-bus transfer protocol and is acting as slave device. The 7 bits unique slave address is 1000000 and supports receiving / transmitting speed up to 400kHz.
5.1 I2C bus overview
Only two wires SDA (serial data) and SCL (serial clock) carry information between the devices connected
to the I2C bus. Normally both SDA and SCL lines are open collector structure and pull high by external pull-up resistors.
Only the master can initiates a transfer (start), generates clock signals, and terminates a transfer (stop). Start and stop condition: A high to low transition of the SDA line while SCL is high defines a start
condition. A low to high transition of the SDA line while SCL is high defines a stop condition. Please refer to Fig 5.1.
Valid data: The data on the SDA line must be stable during the high period of the SCL clock. Within each
byte, MSB is always transferred first. Read/write control bit is the LSB of the first byte. Please refer to Fig 5.2.
Both the master and slave can transmit and receive data from the bus. Acknowledge: The receiving device should pull down the SDA line during high period of the SCL clock
line when a complete byte was transferred by transmitter. In the case of a master received data from a slave, the master does not generate an acknowledgment on the last byte to indicate the end of a master read cycle.
SDA
SCL S Start Condition P Stop Condition
Fig 5.1 Start and Stop Conditions
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SDA
DATA STABLE
DATA CHANGE ALLOWED
SCL
Fig 5.2 Valid Data 5.2 Data Transfer Format
5.2.1 Master transmits data to slave (write cycle)

S : Start A : Acknowledge by slave P : Stop RW : The LSB of 1ST byte to decide whether current cycle is read or write cycle. RW=1 read cycle, RW=0 write cycle.
SUBADDRESS : The address values of PAS106BCB-283/PAS106BBB-283 internal control registers register description)
1ST BYTE 2ND BYTE n BYTEs + A
(Please refer to PAS106BCB-283/PAS106BBB-283
S
SLAVE ID (7 BIT)
RW
A
SUBADDRESS (8 BIT)
A
DATA
A
DATA
A
P
MSB
LSB=0
During write cycle, the master generates start condition and then places the 1st byte data that are combined slave address (7 bits) with a read/write control bit to SDA line. After
slave(PAS106BCB-283/PAS106BBB-283) issues acknowledgment, the master places 2nd byte (sub-address) data on SDA line. Again follow the PAS106BCB-283/PAS106BBB-283 acknowledgment, the master places the 8 bits data on SDA line and transmit to PAS106BCB-283/PAS106BBB-283 control register (address was
nd assigned by 2 byte). After PAS106BCB-283/PAS106BBB-283 issue acknowledgment, the master can
generate a stop condition to end of this write cycle. In the condition of multi-byte write, the PAS106BCB-283/PAS106BBB-283 sub-address is automatically increment after each DATA byte transferred.
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The data and A cycles is repeat until last byte write. Every control registers value inside PAS106BCB-283/PAS106BBB-283 can be programming via this way. (Please refer to Fig 5.3.)
5.2.2 Slave transmits data to master (read cycle)
The sub-address was taken from previous write cycle The sub-address is automatically increment after each byte read Am : Acknowledge by master Note there is no acknowledgment from master after last byte read
1ST BYTE SLAVE ADDRESS (7 BITS)
2ND BYTE
n BYTE
S
RW
A
DATA (8 BIT)
Am
DATA
Am
DATA
1
P
NO ACK IN LAST BYTE
During read cycle, the master generates start condition and then place the 1st byte data that are combined slave address (7 bits) with a read/write control bit to SDA line. After issue acknowledgment, 8 bits DATA was also placed on SDA line by PAS106BCB-283/PAS106BBB-283. The 8 bit data was read from PAS106BCB-283/PAS106BBB-283 internal control register that address was assigned by previous write cycle. Follow the master acknowledgment, the PAS106BCB-283/PAS106BBB-283 place the next 8 bits data (address is increment automatically) on SDA line and then transmit to master serially. The DATA and Am cycles is repeat until the last byte read. After last byte read, Am is no longer generated by master but instead by keep SDA line high. The slave (PAS106BCB-283/PAS106BBB-283) must releases SDA line to master to generate STOP condition. (Please refer to Fig 5.3.)
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SDA
SCL 1-7 8 9 1-7 8 Data 9 1-7 Data 8 9 P ACK Stop from Condition Receiver S Start Address R/W ACK from Condition Receiver
ACK from Receiver Fig 5.3 Data Trans fer Format
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5.3 I2C Bus Timing SDA tf tLOWtr SCL S tf tSU;DAT tHD;STA tSP tr tBUF
S r tHD;STA tHD;DAT tHIGH tSU;STA
tSU;STO P
S
5.4 I2C Bus Timing Specification
STANDARD-MODE PARAMETER SCL clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated. Low period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition Data hold time. For I2C-bus device Data set-up time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Set-up time for STOP condition Bus free time between a STOP and START Capacitive load for each bus line Noise margin at the LOW level for each connected device (including hysteresis) Noise margin at the HIGH level for each connected device (including hysteresis) Note1: It depends on the "high" period time of SCL. SYMBOL MIN. MAX. UNIT
fscl tHD:STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tr tf tSU;STO tBUF Cb VnL VnH
10 4.0 4.7 0.75 4.7 0 250 30 30 4.0 4.7 1 0.1 VDD 0.2 VDD
400 3.45 N.D. N.D. 15 -
kHz us us us us us ns ns(note1) ns(note1) us us pF V V
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6. Specifications
Absolute Maximum Ratings Symbol Vdd Vin Vout Tstg Parameter DC supply voltage DC input voltage DC output voltage Storage temperature Min -0.5 0.5 -0.5 0 Max 3.8 Vdd+0.5 Vdd+0.5 70 Unit V V V J
DC Electrical Characteristics (VDD=3.3V5%, Ta=0C~40C ) Symbol Type :PWR VDD Analog and digital operating voltage 3.15 3.3 35 2.0 0 VDD 0.8 10 1.0 Vdd-0.2 0.2 3.45 V mA V V pF uA V V IDD Operating Current Type :IN & I/O Reset and SYSCLK VIH VIL Cin Ilkg VOH VOL Input voltage HIGH Input voltage LOW Input capacitor Input leakage current Output voltage HIGH Output voltage LOW Parameter Min. Typ. Max. Unit
Type : OUT & I/O for PXD0:9, PXCLK, H/VSYNC & SDA, load 10pf, 1.2k[ , 3.3 volts
AC Operating Condition Symbol fsysclk fpxclk Parameter Master clock frequency Pixel clock output frequency Min. 8 Typ. Max. 48 4 Unit MHz MHz
Sensor Characteristics (To be determined) Parameter Photo response non-uniformity Saturation output voltage Dark output voltage Dark signal non-uniformity Sensitivity ( Red channel ) Sensitivity ( Green channel ) Sensitivity ( Blue channel ) Symbol PRNU Vsat. Vdark DSNU R G B Min. Typ. 1.02 1.4 52 1.9 1.2 1.0 0.8 Max. Unit % V mV/sec Lsb V/Lux-sec V/Lux-sec V/Lux-sec Note
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7. Package Information 7.1. Pin Connection Diagram
SYSCLK
24
PXD<1>
PXD<0>
HSYNC
VSYNC
PXCLK
19
20
21
22
23
PXD<2> PXD<3> VSSQ VDDQ PXD<4> PXD<5> PXD<6>
SCL
25
18
26
SDA VDDD VSSD VLRST VSSA VRB VRT
17
27
16
28
15
1
14
2
13
3
12
4 10 9 8 7 6 5
11
VDDAY
CSB
VSSAY
PXD<7>
PXD<8>
-- Bottom View --
PXD<9>
VDDA
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7.2. Package Outline
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7.3. Sensor center and Die&Package center bias
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8. Referencing Circuit Schematic
C3 CSB PXO<9> PXO<8> PXO<7>
C1 C8
0.1uF 0.1uF VDDA
10uF U1 11 10 9 8 7 6 5 C5 1uF C6 1uF
CSB
PXD<7>
PXD<8>
PXD<9>
VSSAY
PXO<6> PXO<5> S1 CSB C2 R1 0.1uF PXO<3> 300k PXO<2> VDDD PXO<4>
12 13 14 15 16 17 18
VDDAY
VDDA
PXD<6> PXD<5> PXD<4> VDDQ VSSQ
VRT VRB VSSX
4 3 2 1 28 300k 27 26 R4 4.7K R5 4.7K VDDD C7 0.1uF R2 300k R3 VDDA
PAS106BCB-283 VLRST PAS106BBB-283 VSSD
VDDD SYSCLK 24 PXD<0> HSYNC VSYNC PXCLK SDA SCL 25 PXD<1>
PXD<3> PXD<2>
19
20
21
22
PXO<1> PXO<0> PXCLK HSYNC VSYNC SYSCLK SCL SDA
23
3.3V
L1 3.3UH VDDD C9 1uF C8 10uF C11 10uF C10 1uF VDDA
L2 DGND
3.3UH AGND
NOTES on capacitors:
1.The 0.1uF caps for power pins lengths LESS than 5mm. MUST have trace
Title pas106-283 Application circuit Size A4 Date: Document Number Jeffery Thursday, May 16, 2002 Sheet 2 of 2 Rev 1.2
2.C4,C5 and C6 for pins 2,3 and 4 MUST have trace lengths LESS than 5mm.
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